Differentiable Logic Gate Networks for Low-Latency EEG Classification on Edge Devices
Diff-Logic models traded floating-point EEG inference for Boolean circuits, cutting edge-device latency while staying competitive on accuracy.
The paper tests Differentiable Logic Gate Networks against matched MLP and BNN baselines across four EEG datasets and two tasks: dementia detection and emotion recognition. On dementia screening, Diff-Logic reached 80.2% Macro F1, 6.8 points above the MLP baseline. On emotion recognition, the MLP did better, but used 2.3x more latency and a 14x larger model on a 7W Jetson Orin Nano CPU. Diff-Logic inference stayed nearly flat as model scale rose 10x, with a peak 2.9x speedup over MLPs at the largest tier. HF Daily Papers' note
The paper tests Differentiable Logic Gate Networks against matched MLP and BNN baselines across four EEG datasets and two tasks: dementia detection and emotion recognition. On dementia screening, Diff-Logic reached 80.2% Macro F1, 6.8 points above the MLP baseline. On emotion recognition, the MLP did better, but used 2.3x more latency and a 14x larger model on a 7W Jetson Orin Nano CPU. Diff-Logic inference stayed nearly flat as model scale rose 10x, with a peak 2.9x speedup over MLPs at the largest tier. HF Daily Papers' note
score 4